1. Field of the Invention
The present invention relates to a signal delay time calculation method of calculating a signal delay in a digital circuit in an LSI, and, more particularly, relates to a signal delay time calculation method of calculating a delay time in a circuit designed by using data items of actual wiring after making a layout pattern of the LSI, and relates to a computer program product for executing the signal delay time calculation method by a computer system.
2. Description of the Related Art
Recently, there is a strong progress toward miniaturization in LSI fields. In this progress, the submicron technology is thereby widely used. Therefore signal delay becomes an important element in LSI design field.
The signal delay is always divided into two parts, a cell delay and a wiring delay. The cell delay is a delay in the cell itself, which is calculated based on the state of the cell, the input signal transition time (or xe2x80x9ctransition timexe2x80x9d in short), and a load capacity of wiring and connected pins to be driven.
The wiring delay is a delay based on a resistance in wiring, and the wiring delay is obtained by subtracting the cell delay from the entire delay.
In general, ELMORE""s equation is used for calculating the wiring delay that has been disclosed in following literatures (A) and (B):
(A) xe2x80x9cThe transient response of damped linear networks with particular regard to wideband amplifiersxe2x80x9d, W. C. Elmore, J. Appl. Physics vol.19, No.1, pp.55-63, January 1948; and
(B) xe2x80x9cSignal Delay in RC Tree Networksxe2x80x9d, J. Rubinstein, P. Penfield Jr., and M. A. Horowitz, IEEE Trans. on Computer-Aided Design, Vol.CAD-2, No.3, July 1983.
However, according to the trend toward the miniaturization in the LSI field where a very-small region smaller in area than a submicron region (named as xe2x80x9cdeep-submicronxe2x80x9d) is used in order to increase the density of an LSI layout, a calculation result of the signal delay using the value xe2x80x9czeroxe2x80x9d as a resistance of wiring becomes not agreed with an actual delay time obtained by considering detailed wiring resistances in the LSI performed by SPICE (Simulation Program with Integrated Circuit Emphasis) and the like. In addition, the use of ELMORE""s equation cannot obtain an adequate approximate-value of the delay time.
There is a phenomenon to reduce the delay time as one reason of the disagreement between these delay times, because a capacitance of a position which is separated from a driver pin through which the wiring is driven is sealed by the wiring resistance and the actual load capacitance relating to a change of the voltage of the output pin from the current voltage to the threshold voltage is smaller than that of the sum of capacitances in the load. By the presence of this phenomenon, the conventional calculation for the signal delay time outputs a larger value of a signal delay time that is greater than the actual value of the signal delay. When this calculated value of the signal delay is used, the actual circuit manufactured enters error operation even if a simulator or a static timing analyzer using the calculated delay value of the signal delay offers a guarantee that this circuit operates correctly without any error operation. An concrete example shown in FIG. 14, because the simulator or the static timing analyzer can use a correct delay value for the clock signal indicated by the waveform 3, and provides a larger delay value for the data bus of the waveform 1, they guarantee that the circuit has no timing error, but, actual operation causes a hold error of the waveform 2, as shown in FIG. 14.
Although it is possible to increase the accuracy of the simulation by using a high accuracy simulator such as SPICE and to eliminate the above conventional drawback, the operation of the high accuracy simulator operates with lower speed. Accordingly, it is impossible to use the high accuracy simulator such as SPICE for a very large-scale integrated circuit because it takes a very long calculation time period. In order to avoid this problem and to calculate the delay time with higher speed, various methods other than the high accuracy simulator such as SPICE have been studied. One of them is AWE (Asymptotic Waveform Evaluation) that was proposed in about 1990. Many papers regarding AWE have been published. The following literature (C) shows a general outline of AWE in detail:
(C) xe2x80x9cAsymptotic Waveform Evaluation for Timing Analysisxe2x80x9d, Lawrence T. Pillage and Ronald A. Rohrer, IEEE Transaction on Computer-Aided Design, Vol.9, No.4, April 1990, 352-366.
Next, a description will be given of a brief explanation of AWE.
In AWE, a signal waveform to be finally calculated is expressed by the following equation (1)                     Const        +                                            ∑              i                        n                    ⁢                      Ki            xc3x97                                          exp                ⁡                                  (                                      Pi                    xc3x97                    t                                    )                                            .                                                          (        1        )            
When Laplace transform is applied to the signal waveform (1), the following equation (2) can be obtained.                               Const          s                +                                            ∑              i                        n                    ⁢                                    Ki                              S                -                Pi                                      .                                              (        2        )            
The equation (2) will be referred to as xe2x80x9cwaveform 1xe2x80x9d.
Next, Laplace transform is applied to an admittance of a target circuit and a power source voltage until Sn. By using the result, the waveform that has been obtained by performing Laplace transform for an actual signal waveform is obtained until Sn. The result will be referred to as xe2x80x9cwaveform 2xe2x80x9d.
In AWE, coefficients of S in both the waveform 1 and the waveform 2 are compared until n-th power, respectively, in order to obtain simultaneous equations. Then, the simultaneous equations are solved in order to obtain the values xe2x80x9cKixe2x80x9d and xe2x80x9cPixe2x80x9d in the equation (2). xe2x80x9cKixe2x80x9d is called to as xe2x80x9cresiduexe2x80x9d, and xe2x80x9cPixe2x80x9d to as xe2x80x9cpolexe2x80x9d.
Section 3.3 (regarding Stability, see page p.357) in the above literature (C) described a case that there is no solution or a positive solution of the real part of the pole xe2x80x9cPixe2x80x9d in lower degree, and therefore AWE can obtain solution in a higher degree rather than the above lower degree. This means that there is no signal waveform of diverging in the calculation for a normal signal waveform and the positive solution of the real part of the pole xe2x80x9cPixe2x80x9d do not become a correct approximation in adequately large time period.
In addition, Section 3.1 (regarding AWE Approximation) in the above literature (C) described a case that a calculation value can be obtained with a third degree order time of xe2x80x9cqxe2x80x9d when a degree of an approximation solution is xe2x80x9cqxe2x80x9d. Thus, because the degree is greater, the amount of the calculation is also increased substantially. Therefore, in concrete application programs, although it is necessary to perform the calculation with a lower degree as lower as possible so that actual real parts of all poles become negative values in order to prevent the increasing of the amount of the calculation, it is difficult to determine the value of the degree correctly and efficiently.
In order to solve the above problem, namely to obtain a method of obtaining a stable solution, there was the following literatures (D) and (E):
(D) xe2x80x9cOn the Stability of Moment-Matching Approximations in Asymptotic Waveform Evaluationxe2x80x9d, D. F. Anastasakis, N. Gopal, S. Y. Kim, and L. T. Pillage, Proceedgins 29th ACM/IEEE Design Automation Conference, 207-212; and
(E) xe2x80x9cMethod and Apparatus for Simulating a Microelectric Interconnect Circuitxe2x80x9d, Pillage et al., U.S. Pat. No.5,379,231.
These literatures (D) and (E) disclosed the method of obtaining a pole by shifting a moment and then of obtaining a residue by using a moment that has not been shifted if it is difficult to obtain a stable solution. However, this method requires the calculation for moments as large as possible by the shift value under a prediction where a correct value can be obtained. This raises a problem to take a long calculation time.
There is a literature (F) to make a model of a cell using AWE.
(F) xe2x80x9cA Gate-Delay Model for High-Speed CMOS Circuitsxe2x80x9d, Florentin Dartu, Noel Menezes, Jessica Qian and Lawrence T. Pillage, Proceedings 31st ACM/IEEE Design Automation Conference, 576-580.
FIGS. 15 and 16 show a model of an output pin in a cell. It is approximated that the output pin 100 in the cell shown in FIG. 15 is connected to the power source voltage Vd 101 through an internal resistance Rd102. Hereinafter, the voltage at the output pin 100 of the cell in the model shown in FIG. 15 and FIG. 16 is designated by Vdrive. FIG. 16 shows the change of the power source voltage Vd101 shown in FIG. 15 having a signal transition time xcex94T whose change is started at Time t0 when an input signal (designated by a dotted line) crosses a threshold voltage at Time zero. However, it is not always necessary to define the effective capacitance (Ceff) as a capacitance having a current that is equal in amount to a mean current between xcex94T of the power source voltage of a ramp waveform in the cell, as described in the above literature (F), for the effective capacitance (Ceff). It is possible to define the effective capacitance Ceff as a capacitance having a time that is equal to the time at which the voltage on the output pin 100 driving the wiring crosses the threshold voltage Vth.
Further, the method disclosed in the literature (F) make a request to measure and obtain cell parameters t0, xcex94T, and Rd as the characteristics of a cell. However, it has more convenience that these cell parameters are calculated based on the characteristic values in the cell that have been measured.
The following literature (G) disclosed the method to obtain the cell parameters t0 and xcex94T based on already-measured values.
(G) xe2x80x9cA delay Calculation System for Deep Submicron Designxe2x80x9d, Oshima et al., P43-49, TECHNICAL REPORT of IEICE, VLD98-137 (1999-03),.
However, Equation (3) used in the above literature (G) is based on the hypothesize in which the waveform of an output signal is a ramp waveform. This arises a larger error. In addition, the above literature (F) also described that an internal resistance value is calculated from the waveform of an output signal. Furthermore, the above literature (G) did not report that the internal resistance Rd is converted from an existing characteristic value of a cell that has already been measured. In order to calculate the internal resistance Rd based on the the waveform, it must be necessary to measure the characteristic of the cell again. However, it is a convenience that the cell parameters such as the internal resistance Rd, the value t0, and the value xcex94t are calculated based on the characteristic value of the cell that has already been measured.
As described above, in the conventional AWE methods to calculate a signal delay time in LSI, it is necessary to obtain the solution with a degree as lower as possible in order to reduce the amount of calculation. However, it is difficult to determine the value of the degree in order to obtain a correct solution. There were various methods to solve this conventional drawback, they require much calculation time.
On the other hand, in the conventional method to make a model based on AWE, cell parameters to be used in calculation can be obtained from existing measured-values. However, because the hypothesize in which the waveform of the output signal is a ramp (shaped) waveform is used, there is a drawback that an error of each cell parameter becomes large. In order to calculate one cell parameter based on the waveform of the output signal, it is necessary to measure the characteristic of the cell again.
Accordingly, an object of the present invention is, with due consideration to the drawbacks of the conventional technique, to provide a signal delay time calculation method of calculating a signal delay time in LSI and to provide a computer program product for executing this method by a computer system capable of easily and preciously calculate the signal delay time in LSI with short time.
In accordance with an embodiment of the present invention, a signal delay time calculation method is executed based on Asymptotic Waveform Evaluation (AWE) of calculating an approximate signal delay time in a semiconductor integrated circuit (LSI) by calculating a voltage waveform of a signal by using terms of an admittance up to n-th order obtained by performing Laplace transform for the LSI. This signal delay time calculation method comprises: first step of calculating an admittance of the LSI by performing Laplace transform; second step of calculating a first voltage waveform obtained by Laplace transform of a power source voltage for driving the admittance obtained by Laplace transform in the first step; third step of calculating a second voltage waveform obtained by Laplace transform of voltage at an optional point in the LSI based on the admittance obtained in the first step and the first voltage waveform obtained in the second step; fourth step of calculating a real-time approximate voltage waveform of the second voltage waveform by obtaining poles and residues of the second voltage waveform; fifth step of calculating a signal delay time in the LSI based on the real-time voltage waveform obtained in the fourth step; and sixth step of judging whether the signal delay time obtained in the fifth step is within an acceptable precision range when one or more poles obtained in the fourth step include a real-number part of more than zero.